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Preliminary Technical Data
Serial Ports
ADSP-21462/ADSP-21465/ADSP-21467/ADSP-21469
To determine whether communication is possible between two
devices at clock speed n, the following specifications must be
confirmed: 1) frame sync delay and frame sync setup and hold,
2) data delay and data setup and hold, and 3) SCLK width.
Table 31. Serial Ports—External Clock
Serial port signals (SCLK, FS, Data Channel A, Data Channel B)
are routed to the DAI_P20–1 pins using the SRU. Therefore, the
timing specifications provided below are valid at the
DAI_P20–1 pins.
Parameter
Min
Max
Unit
Timing Requirements
t SFSE 1
FS Setup Before SCLK
t HFSE 1
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
TBD
TBD
TBD
TBD
ns
ns
t SDRE
1
Receive Data Setup Before Receive SCLK
TBD
TBD
ns
t HDRE 1
t SCLKW
t SCLK
Receive Data Hold After SCLK
SCLK Width
SCLK Period
TBD
TBD
TBD
TBD
TBD
TBD
ns
ns
ns
Switching Characteristics
TBD
TBD
t DFSE 2
FS Delay After SCLK
TBD
t HOFSE 2
(Internally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
TBD
ns
(Internally Generated FS in either Transmit or Receive Mode)
TBD
TBD
ns
t DDTE 2
Transmit Data Delay After Transmit SCLK
TBD
TBD
ns
t HDTE
2
Transmit Data Hold After Transmit SCLK
TBD
TBD
ns
1
2
Referenced to sample edge.
Referenced to drive edge.
Table 32. Serial Ports—Internal Clock
Parameter
Min
Max
Unit
Timing Requirements
t SFSI 1
FS Setup Before SCLK
t HFSI 1
(Externally Generated FS in either Transmit or Receive Mode)
FS Hold After SCLK
(Externally Generated FS in either Transmit or Receive Mode)
TBD
TBD
TBD
TBD
ns
ns
t SDRI 1
Receive Data Setup Before SCLK
TBD
TBD
ns
t HDRI
1
Receive Data Hold After SCLK
TBD
TBD
ns
Switching Characteristics
TBD
TBD
t DFSI 2
t HOFSI 2
FS Delay After SCLK (Internally Generated FS in Transmit Mode)
FS Hold After SCLK (Internally Generated FS in Transmit Mode)
TBD
TBD
TBD
TBD
ns
ns
t DFSIR
2
FS Delay After SCLK (Internally Generated FS in Receive Mode)
TBD
TBD
ns
t HOFSIR 2
t DDTI 2
FS Hold After SCLK (Internally Generated FS in Receive Mode)
Transmit Data Delay After SCLK
TBD
TBD
TBD
TBD
ns
ns
t HDTI
2
Transmit Data Hold After SCLK
TBD
TBD
ns
t SCKLIW
Transmit or Receive SCLK Width
TBD
TBD
ns
1
2
Referenced to the sample edge.
Referenced to drive edge.
Rev. PrC
| Page 35 of 62 | January 2009
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